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NXP Semiconductors /LPC5410x /ADC0 /INTEN

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Interpret as INTEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)SEQA_INTEN 0 (DISABLED)SEQB_INTEN 0 (DISABLED)OVR_INTEN 0 (DISABLED)ADCMPINTEN0 0ADCMPINTEN1 0ADCMPINTEN2 0ADCMPINTEN3 0ADCMPINTEN4 0ADCMPINTEN5 0ADCMPINTEN6 0ADCMPINTEN7 0ADCMPINTEN8 0ADCMPINTEN9 0ADCMPINTEN10 0ADCMPINTEN11 0RESERVED

OVR_INTEN=DISABLED, SEQB_INTEN=DISABLED, SEQA_INTEN=DISABLED, ADCMPINTEN0=DISABLED

Description

ADC Interrupt Enable Register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.

Fields

SEQA_INTEN

Sequence A interrupt enable.

0 (DISABLED): Disabled. The sequence A interrupt/DMA trigger is disabled.

1 (ENABLED): Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register.
SEQB_INTEN

Sequence B interrupt enable.

0 (DISABLED): Disabled. The sequence B interrupt/DMA trigger is disabled.

1 (ENABLED): Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register.
OVR_INTEN

Overrun interrupt enable.

0 (DISABLED): Disabled. The overrun interrupt is disabled.

1 (ENABLED): Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted.
ADCMPINTEN0

Threshold comparison interrupt enable for channel 0.

0 (DISABLED): Disabled.

1 (OUTSIDE_THRESHOLD): Outside threshold.

2 (CROSSING_THRESHOLD): Crossing threshold.

3 (RESERVED): Reserved
ADCMPINTEN1

Channel 1 threshold comparison interrupt enable. See description for channel 0.
ADCMPINTEN2

Channel 2 threshold comparison interrupt enable. See description for channel 0.
ADCMPINTEN3

Channel 3 threshold comparison interrupt enable. See description for channel 0.
ADCMPINTEN4

Channel 4 threshold comparison interrupt enable. See description for channel 0.
ADCMPINTEN5

Channel 5 threshold comparison interrupt enable. See description for channel 0.
ADCMPINTEN6

Channel 6 threshold comparison interrupt enable. See description for channel 0.
ADCMPINTEN7

Channel 7 threshold comparison interrupt enable. See description for channel 0.
ADCMPINTEN8

Channel 8 threshold comparison interrupt enable. See description for channel 0.
ADCMPINTEN9

Channel 9 threshold comparison interrupt enable. See description for channel 0.
ADCMPINTEN10

Channel 10 threshold comparison interrupt enable. See description for channel 0.
ADCMPINTEN11

Channel 21 threshold comparison interrupt enable. See description for channel 0.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data